Semiconductor processing can include many lithography and etch steps, where a pattern defined in a lithographic mask is exposed to a light source, resulting in the printing of the pattern on a photoresist film deposited on a layer stack that is built up layer by layer on a semiconductor wafer. After development of the resist, etching reproduces the pattern in a layer of the stack, for example for realizing a metal conductor pattern in a level of the back-end-of-line stack of an integrated circuit chip. Feature dimensions of the printed and etched patterns in present day processing technology are on the order of nanometers, and the monitoring of the printed/etched features can require specific metrology tools.
The dependence of the feature dimensions on a plurality of lithographic parameters has been the subject of intensive study. Methods for monitoring the litho-process can include establishing a parametric model that correlates dimensions of specific control patterns to the set values of dose and focus applied in the lithography tool. The measurement of dimensions of the control patterns can take place via Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM), optical microscopy, or other means. The determination of feature dimensions by SEM or AFM is however time-consuming and often destructive. Also, the control patterns applied in this way are typically not design rule compatible. As a result, the influence of etch parameters on the manufactured pattern is generally not taken into account. There is a need therefore for alternative methods that allow a more reliable and more non-intrusive way of verifying a pattern after lithography and etching.